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INTEGRATED CIRCUITS
74LVC10A Triple 3-input NAND gate
Product specification 1998 Apr 28
Philips Semiconductors
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10A
FEATURES
* Wide supply voltage range of 1.2 V to 3.6 V * In accordance with JEDEC standard no. 8-1A. * Inputs accept voltages up to 5.5 V * CMOS low power consumption * Direct interface with TTL levels * Output capability: standard * ICC category: SSI
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf v2.5 ns SYMBOL tPHL/tPLH CI CPD PARAMETER Propagation delay nA, nB, nC to nY Input capacitance Power dissipation capacitance per gate
DESCRIPTION
The 74LVC10A is a high performance, low power, low voltage, Si gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC10A provides the 3-input NAND function.
CONDITIONS CL = 50 pF; VCC = 3.3 V VI = GND to VCC1
TYPICAL 3.9 5.0 26
UNIT ns pF pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi ) (CL x VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74LVC10A D 74LVC10A DB 74LVC10A PW NORTH AMERICA 74LVC10A D 74LVC10A DB 74LVC10APW DH DWG NUMBER SOT108-1 SOT337-1 SOT402-1
PIN CONFIGURATION
1A 1B 2A 2B 2C 2Y GND 1 2 3 4 5 6 7 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 8 3A
LOGIC SYMBOL
1 2 13 1A 1B 1C 1Y 12
3 4 5
2A 2B 2C 2Y 6
9 3Y 10 11
3A 3B 3C 3Y 8
SV00416 SV00417
PIN DESCRIPTION
PIN NUMBER 1, 3, 9 2, 4, 10 7 12, 6, 8 13, 5, 11 14 1998 Apr 28 SYMBOL 1A - 3A 1B - 3B GND 1Y - 3Y 1C - 3C VCC NAME AND FUNCTION Data inputs Data inputs Ground (0 V) Data outputs Data inputs Positive supply voltage 2 853-1973 19308
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10A
LOGIC SYMBOL (IEEE/IEC)
1 2 13 3 4 5 9 10 11 & 12 &
FUNCTION TABLE
INPUTS nA L L L L H H H H NOTES: H = HIGH voltage level L = LOW voltage level
Y
OUTPUTS nC L H L H L H L H nY H H H H H H H L
nB L L H H L L H H
6
&
8
SV00418
LOGIC DIAGRAM (ONE GATE)
A B C
SV00419
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VCC VI Tamb tr, tf PARAMETER DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) DC input voltage range Operating free-air temperature range Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS MIN 2.7 1.2 0 -40 0 0 MAX 3.6 3.6 5.5 +85 20 10 UNIT V V V C ns/V
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL VCC IIK VI IOK VI/O IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output HIGH or LOW DC input voltage; output 3-State DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI t 0 Note 2 VO uVCC or VO t 0 Note 2 Note 2 VO = 0 to VCC CONDITIONS RATING -0.5 to +6.5 -50 -0.5 to +6.5 "50 -0.5 to VCC +0.5 -0.5 to 6.5 "50 "100 -65 to +150 500 500 UNIT V mA V mA V mA mA C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Apr 28
3
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER VCC = 1.2V VCC = 2.7 to 3.6V VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = -12mA VO OH HIGH level output voltage VCC = 3.0V; VI = VIH or VIL; IO = -100A VCC = 3.0V; VI = VIH or VIL; IO = -12mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL II ICC ICC LOW level output voltage Input leakage current Quiescent supply current Additional quiescent supply current per input pin VCC = 3.0V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 24mA VCC = 3.6V; VI = 5.5V or GND VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V; IO = 0 "0.1 0.1 5 VCC*0.5 VCC*0.2 VCC*0.6 VCC*1.0 0.40 0.20 0.55 "5 10 500 A A A V VCC V TEST CONDITIONS Temp = -40C to +85C MIN VIH VIL HIGH level Input voltage LOW level Input voltage VCC 2.0 GND 0.8 TYP1 MAX V V UNIT
NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF LIMITS SYMBOL tPHL/ tPLH PARAMETER Propagation delay nA, nB, nC to nY WAVEFORM MIN Figures 1, 2 1.5 VCC = 3.3V 0.3V TYP1 3.9 MAX 5.7 VCC = 2.7V MIN 1.5 MAX 6.7 ns UNIT
NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25C.
AC WAVEFORMS
VM = 1.5 V at VCC w 2.7 V VM = 0.5 S VCC at VCC < 2.7 V VOL and VOH are the typical output voltage drop that occur with the output load.
VI nA, nB, nC INPUT GND t PHL VOH nY OUTPUT VOL VM t PLH VM
TEST CIRCUIT
VCC S1 2 * VCC Open GND
500 VI PULSE GENERATOR RT D.U.T. VO
50pF
CL
500
SWITCH POSITION
TEST S1 Open VCC < 2.7V 2.7-3.6V VI VCC 2.7V
SV00420
tPLH/tPHL
Figure 1. Input (nA, nB, nC) to output (nY) propagation delays.
SV00903
Figure 2. Load circuitry for switching times.
1998 Apr 28
4
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10A
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
1998 Apr 28
5
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10A
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
1998 Apr 28
6
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10A
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
1998 Apr 28
7
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 07-98 9397-750-04482
Philips Semiconductors
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